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Flip-Flops/Counters MCQs

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71. An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.
A. HIGHs are applied simultaneously to both inputs S and R
B. LOWs are applied simultaneously to both inputs S and R
C. a LOW is applied to the S input while a HIGH is applied to the R input
D. a HIGH is applied to the S input while a LOW is applied to the R input
Discussion
72. On a J-K flip-flop, when is the flip-flop in a hold condition?
A. J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1
Discussion
73. The output pulse width for a 555 monostable circuit with R1 = 3.3 k and C1 = 0.02 F is ________.
A. 7.3 s
B. 73 s
C. 7.3 ms
D. 73 ms
Discussion
74. Edge-triggered flip-flops must have:
A. very fast response times.
B. at least two inputs to handle rising and falling edges.
C. a pulse transition detector.
D. active-LOW inputs and complemented outputs.
Discussion
75. As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:
A. very long.
B. very short.
C. at a maximum value to enable the input control signals to stabilize.
D. of no consequence as long as the levels are within the determinate range of value.
Discussion
76. A positive edge-triggered D flip-flop will store a 1 when ________.
A. the D input is HIGH and the clock transitions from HIGH to LOW
B. the D input is HIGH and the clock transitions from LOW to HIGH
C. the D input is HIGH and the clock is LOW
D. the D input is HIGH and the clock is HIGH
Discussion
77. If an input is activated by a signal transition, it is ________
A. edge-triggered
B. toggle triggered
C. clock triggered
D. noise triggered
Discussion

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