134. A J-K flip-flop is in the toggle condition when
A.J= 1, K=0
B. J = 1, K = 1
C. J = 0, K = 0
D. J = 0, K = 1

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135. A J-K flip-flop with J 1 and K = 1 has a 10 kHz clock input. The Q = output is,
A. constantly LOW
B. constantly HIGH
C. a 5 kHz square wave
D. a 10 kHz square wave

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136. For an edge-triggered D flip-flop,
A. a change in the state of the flip-flop can occur only at a clock pulse edge
B. the state the flip-flop goes to depends on the D input
C. the output follows the input at each clock pulse
D. all of these answers

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137. The flip-flop shown in Fig. 7.6 logically behaves as
A. a D flip-flop
B. a J-K flip'-flop
C. a I flip-flop
D. an R-S flip-flop

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138. A J-K flip-flop is a device to
A. divide the frequency by 2
B. divide the frequency by 4
C. generate waveform of tsame frequency as that of the input
D. cannot be used for frequency division

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139. A 1 Its pulse can be converted into a 1 ms pulse by using
A. a monostable multivibrator
B. an astable multivibrator a bistable multivibrator
C.(e) a J-K flip-flop
D. None of these

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140. The following is not a sequential circuit
A. J-K flip-flop
B. counter
C. full-adder
D. shift register

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