15. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________.
A.4 μs
B.40 μs
C.400 μs
D.40 ms

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16. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________.
A.16 s
B.8 s
C.4 s
D.2 s

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17. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
A.ring shift
B.clock
C.Johnson
D.binary

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18. The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?
A.10011100
B.11000000
C.00001100
D.11110000

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19. If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse?
A.11101011
B.00010111
C.11110000
D.00000000

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20. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.
A.right, one
B.right, two
C.left, one
D.left, three

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21. How many clock pulses will be required to completely load serially a 5-bit shift register?
A.2
B.3
C.4
D.5

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